An information processing apparatus such as a server may have a reconfigurable circuit such as a field programmable gate array (FPGA) capable of rewriting a logic circuit. A logic circuit for executing a process is written in the FPGA, for example, at the time of starting up the information processing apparatus. In addition, the logic circuit written in the FPGA is reconfigured, for example, by dynamic reconfiguration in which the logic circuit is changed during the operation of the circuit.
For example, when an information processing apparatus having an FPGA sequentially executes jobs registered in a queue, when no logic circuit for executing the jobs is written in the FPGA, the information processing apparatus writes a logic circuit in the FPGA and uses the logic circuit written in the FPGA to execute the jobs. In this connection, there has been proposed an information processing apparatus that changes the processing order of jobs registered in a queue when at least one of an FPGA area where a logic circuit for executing the jobs is written and a memory area used for the jobs cannot be secured (see, e.g., Japanese Laid-Open Patent Publication No. 2016-206729).
For example, in the FPGA, the time required for rewriting the logic circuit is longer than the time taken for the logic circuit to execute a process. For this reason, when plural processes are executed while rewriting the logic circuit in the FPGA, the time taken from the start of the first process among the plural processes to the completion of the last process increases with the increase in the number of times of dynamic reconfiguration. That is, as the number of times of dynamic reconfiguration increases, the performance of the information processing apparatus is deteriorated.
Related techniques are disclosed in, for example, Japanese Laid-Open Patent Publication No. 2016-206729.